1. Field of the Invention
The present invention relates to cell array circuitry for use, for example, in digital-to-analog converters (DACs).
2. Description of the Related Art
FIG. 1 of the accompanying drawings shows parts of a conventional digital-to-analog converter (DAC) of the so-called "current-steering" type. The DAC 1 is designed to convert an m-bit digital input word (D1-Dm) into a corresponding analog output signal.
The DAC 1 includes a plurality (n) of identical current sources 2.sub.1 to 2.sub.n where n=2.sup.m -1. Each current source 2 passes a substantially constant current I. The DAC 1 further includes a plurality of differential switching circuits 4.sub.1 to 4.sub.n corresponding respectively to the n current sources 2.sub.1 to 2.sub.n. Each differential switching circuit 4 is connected to its corresponding current source 2 and switches the current I produced by the current source either to a first terminal, connected to a first connection line A of the converter, or a second terminal connected to a second connection line B of the converter.
Each differential switching circuit 4 receives one of a plurality of control signals T1 to Tn (called "thermometer-coded signals" for reasons explained hereinafter) and selects either its first terminal or its second terminal in accordance with the value of the signal concerned. A first output current I.sub.A of the DAC 1 is the sum of the respective currents delivered to the differential-switching-circuit first terminals, and a second output current I.sub.B of the DAC 1 is the sum of the respective currents delivered to the differential-switching-circuit second terminals.
The analog output signal is the voltage difference V.sub.A -V.sub.B between a voltage V.sub.A produced by sinking the first output current I.sub.A of the DAC 1 into a resistance R and a voltage V.sub.B produced by sinking the second output current I.sub.B of the converter into another resistance R.
In the FIG. 1 DAC the thermometer-coded signals T1 to Tn are derived from the binary input word D1-Dm by a binary-thermometer decoder 6. The decoder 6 operates as follows.
When the binary input word D1-Dm has the lowest value the thermometer-coded signals T1-Tn are such that each of the differential switching circuits 4.sub.1 to 4.sub.n selects its second terminal so that all of the current sources 2.sub.1 to 2.sub.n are connected to the second connection line B. In this state, V.sub.A =0 and V.sub.B =nIR. The analog output signal V.sub.A -V.sub.B =-nIR.
As the binary input word D1-Dm increases progressively in value, the thermometer-coded signals T1 to Tn produced by the decoder 6 are such that more of the differential switching circuits select their respective first terminals (starting from the differential switching circuit 4.sub.1) without any differential switching circuit that has already selected its first terminal switching back to its second terminal. When the binary input word D1-Dm has the value i, the first i differential switching circuits 4.sub.1 to 4.sub.i select their respective first terminals, whereas the remaining n-i differential switching circuits 4.sub.i+1 to 4.sub.n select their respective second terminals. The analog output signal V.sub.A -V.sub.B is equal to (2i-n)IR.
FIG. 2 shows an example of the thermometer-coded signals generated for a three-bit binary input word D1-D3 (i.e. in this example m=3). In this case, seven thermometer-coded signals T1 to T7 are required (n=2.sup.m -1=7).
As FIG. 2 shows, the thermometer-coded signals T1 to Tn generated by the binary-thermometer decoder 6 follow a so-called thermometer code in which it is known that when an rth-order signal Tr is activated (set to "1"), all of the lower-order signals T1 to Tr-1 will also be activated.
Thermometer coding is popular in DACs of the current-steering type because, as the binary input word increases, more current sources are switched to the first connection line A without any current source that is already switched to that line A being switched to the other line B. Accordingly, the input/output characteristic of the DAC is monotonic and the glitch impulse resulting from a change of 1 in the input word is small.
It will be appreciated that the number of current sources 2 and corresponding differential switching circuits 4 in the FIG. 1 architecture is quite large, particularly when m is greater than or equal to 6. When m=6, for example, n=63, and 63 current sources and 63 differential switching circuits are required. In order to deal with such a large number of current sources, and to enable the thermometer signals to be delivered efficiently to the different differential switching circuits, it has been proposed to arrange the current sources and differential switching circuits as a two-dimensional array of cells, each cell including one current source and its associated differential switching circuit. This arrangement is shown in FIG. 3.
In FIG. 3, 64 cells CL.sub.ij are arranged in an 8.times.8 square array having eight rows and eight columns. In FIG. 3, the first digit of the suffix applied to each cell denotes the row in which the cell is located and the second digit of the suffix denotes the column in which the cell is located. Thus, the cell CL.sub.18 is the cell in row 1, column 8.
Each cell CL.sub.ij includes its own current source 2 and its own differential switching circuit 4. The respective first terminals of the cells of the array are connected together to a first connection line A of the DAC and the respective second terminals of the cells of the array are connected together to a second connection line B of the DAC, as in the FIG. 1 DAC.
In order to avoid having to generate and supply different respective thermometer-coded signals to all the cells of the array, a two-stage decoding process is adopted to convert the binary input word D1-D6 into the respective thermometer-coded control signals T required by the differential switching circuits 4 in the different cells. The first stage of this two-stage decoding process is carried out by respective row and column decoders 12 and 14, and the second stage is carried out by a local decoder 16 provided for each cell.
The three lower-order bits D1-D3 of the binary input word are applied to the column decoder 14 which derives therefrom seven thermometer-coded column selection signals in accordance with FIG. 2. The row decoder 12 receives the three higher-order bits D4-D6 of the input word and derives therefrom seven thermometer-coded row selection signals, also in accordance with FIG. 2. The row and column selection signals are distributed to the cells of the array.
In each cell the local decoder 16 combines the row and column selection signals to derive therefrom the required local control signal T for the differential switching circuit 4 of the cell concerned. In practice, the local decoder 16 in each cell does not need to employ all seven row and column selection signals to produce the required local control signal T. This is because, for any digital input word, the rows of the matrix fall into one of three different states: (1) rows in which the respective differential switching circuits of all cells of the row select the second terminal; (2) rows in which the respective differential switching circuits of all cells of the row select the first terminal; and (3) a (unique) row in which the differential switching circuits of one or more cells of the row select the second terminal whereas the differential switching circuits of one or more other cells of the row select the first terminal. In view of these limited possibilities, it is possible for each local decoder to derive its local control signal T simply by combining two of the row selection signals r.sub.n and r.sub.n+1 and one of the column selection signals c.sub.n.
The numbers allotted to the cells CL.sub.ij in FIG. 3 denote the sequence in which the cells are activated (or controlled) to change from selecting their respective second terminals to selecting their respective first terminals. The activation sequence follows the physical order of the cells in the array, starting from row 1 and activating the cells of that row sequentially in column order, followed by row 2, and so on for each successive row of the array.
One problem which arises in the FIG. 3 arrangement is that, although the output currents of the respective current sources 2 of the different cells of the array should be uniform, in practice the actual output currents of the cells suffer from non-uniformity arising from various causes.
For example, a voltage drop along a power supply line can cause a graded error along a row or column, as shown in FIG. 4(A). In this case, the current sources in the first four cells of the row or column concerned may have negative errors, signifying that each of them produces a below-average output current. These negative errors decrease towards the centre of the row or column concerned. The current sources in the remaining cells 5 to 8 of the row or column concerned have respective positive errors, signifying that each of them produces an above-average output current. These positive errors increase from the centre of the row or column to the end.
Thermal distribution inside a chip including the array can cause a symmetrical error within a row or column, as shown in FIG. 4(B). In this case, the current sources in the end cells 1, 2, 7 and 8 of the row or column have negative errors, whereas the current sources of the central cells 3 to 6 of the row or column have positive errors.
In addition, there can be other types of error such as random errors. The final error distribution for the cell array is produced by superposing all the different error components.
The graded and symmetrical errors shown in FIG. 4(A) and FIG. 4(B) tend to accumulate and result in a large integral linearity error (INL). For example, imagine that the graded error distribution shown in FIG. 4(A) exists within the first row of the cell array shown in FIG. 3. In this case, as cells 1 to 4 are progressively activated (changed from selecting their respective second terminals to selecting their respective first terminals) the negative errors accumulate, amounting to a significant total negative error when the digital input code is 4. Only when cells 5 to 8 are sequentially activated do the positive errors attributable to these cells start to cancel out the large negative error attributable to cells 1 to 4.
Of course the situation is even worse if there are graded errors corresponding to FIG. 4(A) along each of the columns 1 to 8. In this case, as cells 1 to 8 are progressively activated, the largest negative error (the error at position 1 in FIG. 4(A)) occurs for each of the eight cells of row 1. Similarly, in row 2, negative errors corresponding to position 2 in FIG. 4(A) accumulate eight times. Thus, by the time the input code has increased to 32 (corresponding to all of the cells in rows 1 to 4 being activated) the accumulated negative error is very large indeed.
Similar problems arise with the accumulation of symmetrical errors of the kind shown in FIG. 4(B).
Heretofore various proposals have been made which attempt to address the problem of accumulation of graded and symmetrical errors within a row or column of a cell array. For example, IEEE Journal of Solid-State Circuits, Volume 26 No. 4, April 1991, pp. 637-642 discloses a technique referred to as "hierarchical symmetrical switching" for cancelling graded and symmetrical errors within a single row or column. However, such techniques do not provide a fully satisfactory way of dealing with the problem of accumulation of graded and symmetrical errors within different rows and columns of a cell array, i.e. two-dimensional cancellation.